CMOS - CD4017, CMOS Decade Counter, 16-Pin DIP
CD4017B is a 5-stage Johnson counter having 10 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.
These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes on cycle every 10 clock input cycles in the CD4017B and is used to ripple-clock the succeeding device in a multi-device counting chain.
- Fully static operation
- Medium speed operation…10 MHz (typ.) at VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Decade counter/decimal decode display
- Binary counter/decoder
- Frequency division
- Counter control/timers
- Divde-by-N counting
- For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"
|Features||Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode|
|Input type||Standard CMOS|
|Supply voltage (Max) (V)||18|
|Supply voltage (Min) (V)||3|
|Packaging Dimensions||0.775 in. × 0.35 in. × 0.3 in.|
|Weight (Packaging)||0.001 lbs.|